\doxysubsubsubsection{RCCEx CRS Synchro\+Source }
\hypertarget{group___r_c_c_ex___c_r_s___synchro_source}{}\label{group___r_c_c_ex___c_r_s___synchro_source}\index{RCCEx CRS SynchroSource@{RCCEx CRS SynchroSource}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_source_ga92286a7b70051d3ad899b3b4cf7c9840}{RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+SOURCE\+\_\+\+PIN}}~(0x00000000U)
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_source_gaacd7c7d911ef1228fbc7ac4533527026}{RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+SOURCE\+\_\+\+LSE}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga85cd0182bf6bbb7088991ff04c612e20}{CRS\+\_\+\+CFGR\+\_\+\+SYNCSRC\+\_\+0}}
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_source_ga6c53c1d29bb18033c5514f28f2cf9ef8}{RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+SOURCE\+\_\+\+USB1}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab2d2f4200ea8754386aab5947b40721d}{CRS\+\_\+\+CFGR\+\_\+\+SYNCSRC\+\_\+1}}
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_source_ga427f17635c19200b4aeadb4b5a8040ab}{RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+SOURCE\+\_\+\+USB2}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab2d2f4200ea8754386aab5947b40721d}{CRS\+\_\+\+CFGR\+\_\+\+SYNCSRC\+\_\+1}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga85cd0182bf6bbb7088991ff04c612e20}{CRS\+\_\+\+CFGR\+\_\+\+SYNCSRC\+\_\+0}})
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}


\label{doc-define-members}
\Hypertarget{group___r_c_c_ex___c_r_s___synchro_source_doc-define-members}
\doxysubsubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___r_c_c_ex___c_r_s___synchro_source_gaacd7c7d911ef1228fbc7ac4533527026}\index{RCCEx CRS SynchroSource@{RCCEx CRS SynchroSource}!RCC\_CRS\_SYNC\_SOURCE\_LSE@{RCC\_CRS\_SYNC\_SOURCE\_LSE}}
\index{RCC\_CRS\_SYNC\_SOURCE\_LSE@{RCC\_CRS\_SYNC\_SOURCE\_LSE}!RCCEx CRS SynchroSource@{RCCEx CRS SynchroSource}}
\doxysubsubsubsubsubsection{\texorpdfstring{RCC\_CRS\_SYNC\_SOURCE\_LSE}{RCC\_CRS\_SYNC\_SOURCE\_LSE}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___c_r_s___synchro_source_gaacd7c7d911ef1228fbc7ac4533527026} 
\#define RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+SOURCE\+\_\+\+LSE~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga85cd0182bf6bbb7088991ff04c612e20}{CRS\+\_\+\+CFGR\+\_\+\+SYNCSRC\+\_\+0}}}

Synchro Signal source LSE \Hypertarget{group___r_c_c_ex___c_r_s___synchro_source_ga92286a7b70051d3ad899b3b4cf7c9840}\index{RCCEx CRS SynchroSource@{RCCEx CRS SynchroSource}!RCC\_CRS\_SYNC\_SOURCE\_PIN@{RCC\_CRS\_SYNC\_SOURCE\_PIN}}
\index{RCC\_CRS\_SYNC\_SOURCE\_PIN@{RCC\_CRS\_SYNC\_SOURCE\_PIN}!RCCEx CRS SynchroSource@{RCCEx CRS SynchroSource}}
\doxysubsubsubsubsubsection{\texorpdfstring{RCC\_CRS\_SYNC\_SOURCE\_PIN}{RCC\_CRS\_SYNC\_SOURCE\_PIN}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___c_r_s___synchro_source_ga92286a7b70051d3ad899b3b4cf7c9840} 
\#define RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+SOURCE\+\_\+\+PIN~(0x00000000U)}

Synchro Signal source external pin, Available on STM32\+H7 Rev.\+B and above devices only \Hypertarget{group___r_c_c_ex___c_r_s___synchro_source_ga6c53c1d29bb18033c5514f28f2cf9ef8}\index{RCCEx CRS SynchroSource@{RCCEx CRS SynchroSource}!RCC\_CRS\_SYNC\_SOURCE\_USB1@{RCC\_CRS\_SYNC\_SOURCE\_USB1}}
\index{RCC\_CRS\_SYNC\_SOURCE\_USB1@{RCC\_CRS\_SYNC\_SOURCE\_USB1}!RCCEx CRS SynchroSource@{RCCEx CRS SynchroSource}}
\doxysubsubsubsubsubsection{\texorpdfstring{RCC\_CRS\_SYNC\_SOURCE\_USB1}{RCC\_CRS\_SYNC\_SOURCE\_USB1}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___c_r_s___synchro_source_ga6c53c1d29bb18033c5514f28f2cf9ef8} 
\#define RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+SOURCE\+\_\+\+USB1~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab2d2f4200ea8754386aab5947b40721d}{CRS\+\_\+\+CFGR\+\_\+\+SYNCSRC\+\_\+1}}}

Synchro Signal source USB1 SOF (default) \Hypertarget{group___r_c_c_ex___c_r_s___synchro_source_ga427f17635c19200b4aeadb4b5a8040ab}\index{RCCEx CRS SynchroSource@{RCCEx CRS SynchroSource}!RCC\_CRS\_SYNC\_SOURCE\_USB2@{RCC\_CRS\_SYNC\_SOURCE\_USB2}}
\index{RCC\_CRS\_SYNC\_SOURCE\_USB2@{RCC\_CRS\_SYNC\_SOURCE\_USB2}!RCCEx CRS SynchroSource@{RCCEx CRS SynchroSource}}
\doxysubsubsubsubsubsection{\texorpdfstring{RCC\_CRS\_SYNC\_SOURCE\_USB2}{RCC\_CRS\_SYNC\_SOURCE\_USB2}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___c_r_s___synchro_source_ga427f17635c19200b4aeadb4b5a8040ab} 
\#define RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+SOURCE\+\_\+\+USB2~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab2d2f4200ea8754386aab5947b40721d}{CRS\+\_\+\+CFGR\+\_\+\+SYNCSRC\+\_\+1}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga85cd0182bf6bbb7088991ff04c612e20}{CRS\+\_\+\+CFGR\+\_\+\+SYNCSRC\+\_\+0}})}

Synchro Signal source USB2 SOF 